**New approaches for CDM testing**

It is now common knowledge that testing for CDM ESD evaluation is becoming more challenging. Earlier (*In Compliance Magazine,* March 2021), capacitively coupled TLP (CCTLP) was described as an alternative approach. It offers many advantages over the standardized field-induced CDM setup according to the JS002 standard (1). Testing a package, bare chip or wafer is made possible with high reproducibility. The failure correlation between CDM and CCTLP was investigated based on peak current stress levels and not on a charging voltage level (2). When testing with an alternative CDM method, such as CCTLP, to reproduce JS002, the CDM charging voltage must be converted to peak current levels.

A measure of the severity of the CDM stress is the effective capacity *c _{effe}* of a device (3).

*c*characterizes the amount of charge exchanged between DUT and test fixture at a specific stress level (e.g.

_{effe}*V*) in a specific test environment.

_{CDM}Products can be categorized based on *c _{effe}* in a FICDM setup due to its direct relationship with the peak current for a given test voltage, as described in (4).

During a CDM stress, different capacitance values come into play according to the three-capacitance model, as shown in Figure 1.

The three capacitance values determine the effective capacitance *c _{effe}*. The DUT capacity

*c*is defined as the capacitance from the device to the field plane. The static capacitance value for

_{DUUT}*c*was extracted from a Finite Element Method (FEM) simulation according to the three-capacitance model shown in Figure 1. Differences between

_{DUUT}*c*And

_{effe}*c*capacitances either extracted from FEM simulation or calculated as parallel plate capacitance

_{DUUT}*c*(

_{plate}*a*is the area of the DUT, and

*D*is the thickness of the FR4 dielectric layer) are demonstrated based on the metal round coin modules (height 1.27 mm, diameters see table 1).

P1 |
P2 |
JS |
P4 |
JL |
P5 |
P6 |
P7 |
P8 |

2.29 | 4.49 | 8.89 | 18.03 | 25.37 | 36.05 | 43.04 | 51.02 | 62.52 |

*Table 1: Coin diameter in mm, coin height: 1.27 mm*

The FEM simulation of *c _{DUUT}* does not coincide with the simple plate capacitor formula, as edge effects are also taken into account, especially for small devices.

*c*also shows a linear dependence of the area-capacity relationship. Unlike,

_{DUUT}*c*values show saturation with increasing surface area or volume of a DUT. As a result, not only the bottom surface area contributes to the capacity, but also the side walls and therefore the volume.

_{effe}**Impact of device dimensions**

To calculate the CDM discharge current from the volume, the device area is considered as the maximum edge length *a* X *B,* including the pins and mold mass (figure 3). For a bare-die product that does not end up in a final package, the surface area is calculated accordingly based on the edge length of the silicon.

Statistical analysis of CDM test data demonstrates the relevance of device surface area and volume for predicting voltage current levels in a CDM test since the height *H* of the device has a non-negligible influence on the discharge current. A database of more than 15 million CDM waveforms has been used to evaluate the relationship between surface area, volume, peak current and the effective capacitance *c _{effe}*. The surface area and volume of approximately 10,000 different device types can be derived from the package dimensions in the database. For each device type, only the waveforms representing the maximum positive peak current are evaluated

*I*from several CDM discharges for a positive charging voltage level of 500 V. According to the measurement results, the peak current decreases as the height of the device increases.

_{Highlight}This can be demonstrated using the set of nine cylindrical solid metal coins P1 to P8 with different diameters and volumes (see Table 1)(5). The coin reference for the peak current still provides a reasonable orientation for the maximum peak current. Figure 4 shows the dependence on the effective capacity *c _{effe}* on the volume. Very flat packs exceed the coin limit but still give a meaningful value. The coin with the smallest volume and therefore the lowest

*c*reaches the lowest peak current and vice versa. For devices, this means that their

_{effe}*c*with the corresponding flow can be related to the flow of the coins. As shown, the height of the device becomes relevant to the estimation of the voltage current level. Therefore, volume is introduced as the preferred parameter. The volume value can thus be used to estimate the expected peak flow with respect to the coin values, as shown in Figure 5.

_{effe}**Conclusion**

A practical solution to the problem of how to translate CDM objectives to current testing levels is presented. The current CDM test levels are important because they allow the use of alternative CDM test methods, such as CCTLP. The first test proposal is a simple approach, representing the worst case: Increase the CCTLP test voltage until the peak current value is reached on the product pin, shown in Figure 5.

To avoid overtesting, these levels can be reduced based on the second proposal if details of the electrical properties on the package and on the chip are known. *c _{effe}* values can be predicted by FEM simulation even before devices are available.

The full article is published in (6).

**References**

- ANSI/JEDEC/ESDA, “Joint Standard for Electrostatic Discharge Susceptibility Testing – Charged Device Model,” JS-002, 2018
- K. Esmark, R. Gaertner, S. Seidl, F. zur Nieden, H. Wolf, and H. Gieser, “Using CC-TLP to obtain a CDM robustness value,” 37th Symposium on Electrical Overcharge/Electrostatic Discharge ( EOS/ESD) 2015 ), Reno, NV, USA, 2015, pp. 1-10.
- B. C. Atwood, Y. Zhou, D. Clarke, and T. Weyl, “Effect of large device capacitance on FICDM peak current”, 29th Symposium on Electrical Overcharge/Electrostatic Discharge (EOS/ESD), 2007,

Anaheim, CA, USA, 2007, pp. 5A.1‑1‑5A.1-10. - N. Jack, B. Carn and J. Morris, ‘Toward Standardization of Low Impedance Contact CDM’, 41st Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2019, pp. 1-7.
- T. J. Maloney and N. Jack, “CDM tester properties as inferred from waveforms,” in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 3, pp. 792-800, September 2014, doi: 10.1109/TDMR.2014.2316177
- L. Zeitlhoefler, T. Lutz, F. Zur Nieden, K. Esmark, and R. Gaertner, “Voltage-current correlation for CDM testing,”
*45th Annual EOS/ESD Symposium 2023 (EOS/ESD)*Riverside, CA, USA, 2023, pp. 1-11, doi: 10.23919/EOS/ESD58195.2023.10287735